WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTORS!

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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby kormoran » Mon Feb 01, 2016 1:45 am

devsh wrote:you can't use malloc, free, core::array<> (without patching the allocator) or std::vector<> because they allocate memory dynamically and cant guarantee 16byte alignment.


Reason I use C++11 in my project is that cute little alignas keyword... :lol:
Well not the only reason, but a good one among the others :D

http://en.cppreference.com/w/cpp/language/alignas
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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby robmar » Fri Feb 12, 2016 9:46 am

I'm using VS Comunity 2015, fully featured, nice step time displays during debug but only to the ms, however for most projects I have to run it at VC100 level, VS 2010, because the compiler has some bugs with more complex C++; just don´t ugrade, click Cancel, and it runs fine.
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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby kklouzal » Mon Jan 15, 2018 6:45 pm

Hey devsh is there any reason why someone couldn't replace the entire vector/matrix/math implementations with https://glm.g-truc.net?

GLM supports SSE2 all the way up to AVX512 and will detect the appropriate instruction set to use during compilation.
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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby devsh » Tue Jan 16, 2018 8:31 am

The SIMD support is experimental and only for chosen vector/matrix types

GLM_GTX_simd_mat4 SIMD implementation of mat4 type
GLM_GTX_simd_quat SIMD implementation of quat type
GLM_GTX_simd_vec4 SIMD implementation of vec4 type
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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby kklouzal » Tue Jan 16, 2018 3:13 pm

Ah that information is not obviously stated in the manual.

3.4. SIMD support
GLM provides some SIMD optimizations based on compiler intrinsics. These optimizations will be
automatically thanks to compiler arguments. For example, if a program is compiled with Visual Studio using
/arch:AVX, GLM will detect this argument and generate code using AVX instructions automatically when
available.
It’s possible to avoid the instruction set detection by forcing the use of a specific instruction set with one of
the fallowing define: GLM_FORCE_SSE2, GLM_FORCE_SSE3, GLM_FORCE_SSSE3, GLM_FORCE_SSE41, GLM_FORCE_SSE42,
GLM_FORCE_AVX, GLM_FORCE_AVX2 or GLM_FORCE_AVX512.

7.8. Is GLM fast?
Following the Pareto principle where 20% of the code consumes 80% of the execution time, GLM operates
perfectly on the 80% of the code that consumes 20% of the performances. Furthermore, thanks to the
lowp, mediump and highp qualifiers, GLM provides approximations which trade precision for performance.
Finally, GLM can automatically produce SIMD optimized code for functions of its implementation.


Here as you found in the advanced mathmatics section of the 9.2 api it states
GLM provides some SIMD optimizations based on compiler intrinsics. These optimizations will be automatically utilized based on the build environment. These optimizations are mainly available through the extensions GLM_GTX_simd_vec4: SIMD vec4 type and functions and GLM_GTX_simd_mat4: SIMD mat4 type and functions.

That information is a bit outdated at least for the simple fact that intrinsics are no longer separated out into SIMD types but are built into vec4,mat4,quat and that it is are no longer experimental in the API.

Aside from that is there any reason why someone still couldn't or shouldn't replace the entire vector/matrix/math implementations with GLM?
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Re: WANT 4x SPEEDUPS on CPU-side CODE??? SIMD IRRLICHT VECTO

Postby devsh » Tue Jan 16, 2018 4:50 pm

There's obviously a lot of confusion in the documentation, manual etc.

What concerns me most is that I'd have to read their code... to see if the intrinsics are used correctly... there are plenty of times when SIMD can silently fallback on other instructions or do stuff behind your back if you haven't coded it properly.
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